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CY7C11461KV18 Datasheet(PDF) 11 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 11 of 29
Table 3. Truth Table
The truth table for the CY7C11461KV18, CY7C11571KV18, CY7C11481KV18, and CY7C11501KV18 follows.[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L
D(A) at K(t + 1)
D(A+1) at K(t + 1)
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycles;
read data on consecutive K and K rising edges.
L-H
L
H
Q(A) at K(t + 2)
Q(A+1) at K(t + 2)
NOP: No Operation
L-H
H
X
High Z
High Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Table 4. Write Cycle Descriptions
The write cycle description table for CY7C11461KV18 and CY7C11481KV18 follows.[3, 9]
BWS0/
NWS0
BWS1/
NWS1
K
K
Comments
L
L
L–H
During the data portion of a write sequence
CY7C11461KV18
both nibbles (D[7:0]) are written into the device.
CY7C11481KV18
both bytes (D[17:0]) are written into the device.
L
L
L-H During the data portion of a write sequence
CY7C11461KV18
both nibbles (D[7:0]) are written into the device.
CY7C11481KV18
both bytes (D[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
CY7C11461KV18
only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C11481KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
CY7C11461KV18
only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C11481KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
CY7C11461KV18
only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C11481KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
CY7C11461KV18
only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C11481KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
L–H
No data is written into the devices during this portion of a write operation.
H
H
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
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