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CY7C11461KV18 Datasheet(PDF) 9 Page - Cypress Semiconductor
CYPRESS [Cypress Semiconductor]
CY7C11461KV18 Datasheet(HTML) 9 Page - Cypress Semiconductor
/ 29 page
Document Number: 001-53198 Rev. *F
Page 9 of 29
The CY7C11461KV18, CY7C11571KV18, CY7C11481KV18,
and CY7C11501KV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface, which operates with a read
latency of two cycles when DOFF pin is tied HIGH. When DOFF
pin is set LOW or connected to V
, the device behaves in
DDR I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing are referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D
) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q
) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, NWS
pass through input registers controlled by the rising edge of the
input clock (K).
CY7C11481KV18 is described in the following sections. The
CY7C11571KV18, and CY7C11501KV18.
The CY7C11481KV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q
using K as the output timing reference.
On the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q
. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
When read access is deselected, the CY7C11481KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive input clock (K). This enables a transition
between devices without the insertion of wait states in a depth
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D
is latched and stored into the 18-bit write
data register, provided BWS
are both asserted active. On the
subsequent rising edge of the negative input clock (K) the
information presented to D
is also stored into the write data
register, provided BWS
are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C11481KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
The CY7C11481KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C11481KV18 requires two No
Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications require third
NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo clocks are provided on the DDR II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the DDR II+. The timing for
the echo clocks is shown in the Switching Characteristics on
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