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CY7C11461KV18 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 4 of 29
Contents
Pin Configuration ............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
DDR Operation ............................................................ 9
Depth Expansion ......................................................... 9
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
Valid Data Indicator (QVLD) ...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock ................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO) ................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Power Up Sequence in DDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................ 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics .............................................. 21
DC Electrical Characteristics .................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 23
Thermal Resistance ....................................................... 23
Switching Characteristics ............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ..................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ........................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
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