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CY7C10612DV33 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C10612DV33
Description  16-Mbit (1 M 횞 16) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C10612DV33 Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C10612DV33
16-Mbit (1 M × 16) Static RAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-49315 Rev. *B
Revised January 17, 2011
Features
High speed
tAA = 10 ns
Low active power
ICC = 175 mA at 10 ns
Low CMOS standby power
ISB2 = 25 mA
Operating voltages of 3.3 ± 0.3 V
2.0 V data retention
Automatic Power-down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 54-pin TSOP II package
Functional Description
The CY7C10612DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
To read from the device, take Chip Enables (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 9 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C10612DV33 is available in a 54-Pin TSOP II package
with center power and ground (revolutionary) pinout.
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
1M x 16
ARRAY
A0
I/O0 – I/O7
OE
I/O8 – I/O15
CE
WE
BLE
BHE
A9
Logic Block Diagram
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