CY7C1557KV18 datasheet(9/31 Pages) CYPRESS

Part #	CY7C1557KV18

Description	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 31 page

CY7C1546KV18, CY7C1557KV18

CY7C1548KV18, CY7C1550KV18

Document Number: 001-15879 Rev. *I

Page 9 of 31

DOFF

Input

PLL Turn Off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull up through a 10 K

 or less pull up resistor. The device behaves in DDR I mode

when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with DDR I timing.

TDO

Output

Test data out (TDO) for JTAG

TCK

Input

Test clock (TCK) pin for JTAG

TDI

Input

Test data in (TDI) pin for JTAG

TMS

Input

Test mode select (TMS) pin for JTAG

NC

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

Input

Not connected to the die. Can be tied to any voltage level.

NC/288M

Input

Not connected to the die. Can be tied to any voltage level.

VREF

Input-

Reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

VDD

Power Supply Power supply inputs to the core of the device

VSS

Ground

Ground for the device

VDDQ

Power Supply Power supply inputs for the outputs of the device

Pin Definitions (continued)

Pin Name

I/O

Pin Description

[+] Feedback

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CY7C1557KV18 Datasheet(PDF) 9 Page - Cypress Semiconductor

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