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CY7C1393KV18-300BZXC Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1393KV18-300BZXC Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 31 page  CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-58907 Rev. *B Revised February 25, 2011 Features ■ 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW ■ 1.8 V core power supply with HSTL inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output voltage (1.4 V–VDD) ❐ Supports both 1.5 V and 1.8 V I/O supply ■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement Configurations CY7C1392KV18 – 2 M x 8 CY7C1992KV18 – 2 M x 9 CY7C1393KV18 – 1 M x 18 CY7C1394KV18 – 512 K x 36 Functional Description The CY7C1392KV18, CY7C1992KV18, CY7C1393KV18, and CY7C1394KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392KV18, two 9-bit words in the case of CY7C1992KV18, two 18-bit words in the case of CY7C1393KV18, and two 36-bit words in the case of CY7C1394KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Table 1. Selection Guide Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Maximum operating frequency 333 300 250 200 167 MHz Maximum operating current x8 440 420 370 330 300 mA x9 440 420 370 330 300 x18 450 430 380 340 310 x36 560 520 460 400 360 [+] Feedback |
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