CY7C1380D-167BZC datasheet(2/33 Pages) CYPRESS

Part #	CY7C1380D-167BZC

Description	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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2 / 33 page

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Document Number: 38-05543 Rev. *I

Page 2 of 33

Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512 K × 36)

Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1 M × 18)

ADDRESS

REGISTER

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

Q1

Q0

ADSP

ADSC

MODE

BWE

GW

CE 1

CE 2

CE 3

OE

ENABLE

REGISTER

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

E

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

BW B

BW C

BW D

BW A

MEMORY

ARRAY

DQs

DQP A

DQP B

DQP C

DQP D

SLEEP

CONTROL

ZZ

A[1:0]

2

DQ A ,DQP A

BYTE

WRITE REGISTER

DQ B , DQP B

BYTE

WRITE REGISTER

DQ C , DQP C

BYTE

WRITE REGISTER

DQ D ,DQP D

BYTE

WRITE REGISTER

DQ A ,DQP A

BYTE

WRITE DRIVER

DQ B , DQP B

BYTE

WRITE DRIVER

DQ C , DQP C

BYTE

WRITE DRIVER

DQ D ,DQP D

BYTE

WRITE DRIVER

A0, A1, A

ADDRESS

REGISTER

ADV

CLK

BURST

COUNTER AND

LOGIC

Q1

ADSC

BW B

BW A

CE 1

DQ B, DQP B

WRITE REGISTER

DQ A,DQP A

WRITE REGISTER

ENABLE

REGISTER

OE

SENSE

MEMORY

ARRAY

2

CE2

CE3

GW

BWE

PIPELINED

ENABLE

DQs

DQP A

DQP B

OUTPUT

INPUT

DQ A,DQP A

WRITE DRIVER

OUTPUT

BUFFERS

DQ B, DQP B

WRITE DRIVER

ZZ

SLEEP

CONTROL

Note

3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).

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