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CY7C1381D-133AXC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1381D-133AXC Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 34 page  CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F Document Number: 38-05544 Rev. *I Page 10 of 34 Three synchronous chip selects (CE1, CE2, CE3 [5]) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 [5] are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and later presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs with a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 [5] are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table for Read/Write on page 13 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. All I/O are tristated during a byte write. As this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 [5] are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core The information presented to DQ[A:D] is written into the specified address location. Byte writes are allowed. All I/O are tristated when a write is detected, even a byte write. Because this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Burst Sequences CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3 [5], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Table 1. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Table 2. Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Note 5. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable. [+] Feedback |
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