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CY7C1314CV18-200BZI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1314CV18-200BZI
Description  18-Mbit QDR짰 II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1314CV18-200BZI Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1312CV18
CY7C1314CV18
Document #: 001-07164 Rev. *H
Page 9 of 26
Truth Table
The truth table for CY7C1312CV18, and CY7C1314CV18 follows.[2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t)
D(A + 1) at K(t)
Read Cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)
 Q(A + 1) at C(t + 2) 
NOP: No Operation
L-H
H
H
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1312CV18 follows.[2, 8]
BWS0 BWS1
K
K
Comments
L
L
L–H
During the data portion of a write sequence
Both bytes (D[17:0]) are written into the device.
L
L
L-H During the data portion of a write sequence
Both bytes (D[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
L–H
No data is written into the devices during this portion of a write operation.
H
H
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
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