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CY7C1315CV18-250BZI Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C1315CV18-250BZI
Description  18-Mbit QDR짰 II SRAM 4-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1315CV18-250BZI Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C1313CV18
CY7C1315CV18
Document Number: 001-07165 Rev. *G
Page 5 of 29
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1313CV18
 D[17:0]
CY7C1315CV18
 D[35:0]
WPS
Input-
Synchronous
Write Port Select
 Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
 Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1313CV18
 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315CV18
 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
1M x 18 (4 arrays each of 256K x 18) for CY7C1313CV18 and 512K x 36 (4 arrays each of 128K x 36)
for CY7C1315CV18. Therefore, only 18address inputs are needed to access the entire memory array of
CY7C1313CV18 and 17 address inputs for CY7C1315CV18. These inputs are ignored when the appro-
priate port is deselected.
Q[x:0]
Output-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1313CV18
 Q[17:0]
CY7C1315CV18
 Q[35:0]
RPS
Input-
Synchronous
Read Port Select
 Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 23.
CQ
Echo Clock
CQ is referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 23.
ZQ
Input
Output Impedance Matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
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