CY7C1318BV18 datasheet(4/31 Pages) CYPRESS

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CY7C1318BV18 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part #	CY7C1318BV18

Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1318BV18, CY7C1320BV18

Document Number: 38-05621 Rev. *G

Page 4 of 31

Contents

Pin Configuration ............................................................. 5

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5

Pin Definitions .................................................................. 7

Functional Overview ........................................................ 9

Read Operations ......................................................... 9

Write Operations ......................................................... 9

Byte Write Operations ................................................. 9

Single Clock Mode ...................................................... 9

DDR Operation ............................................................ 9

Depth Expansion ......................................................... 9

Programmable Impedance ........................................ 10

Echo Clocks .............................................................. 10

DLL ............................................................................ 10

Application Example ...................................................... 10

Truth Table ...................................................................... 11

Burst Address Table ...................................................... 11

Write Cycle Descriptions ............................................... 11

Write Cycle Descriptions ............................................... 12

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13

Disabling the JTAG Feature ...................................... 13

Test Access Port—Test Clock ................................... 13

Test Mode Select (TMS) ........................................... 13

Test Data-In (TDI) ..................................................... 13

Test Data-Out (TDO) ................................................. 13

Performing a TAP Reset ........................................... 13

TAP Registers ........................................................... 13

TAP Instruction Set ................................................... 13

TAP Controller State Diagram ....................................... 15

TAP Controller Block Diagram ...................................... 16

TAP Electrical Characteristics ...................................... 16

TAP AC Switching Characteristics ............................... 17

TAP Timing and Test Conditions .................................. 17

Identification Register Definitions ................................ 18

Scan Register Sizes ....................................................... 18

Instruction Codes ........................................................... 18

Boundary Scan Order .................................................... 19

Power Up Sequence in DDR-II SRAM ........................... 20

Power Up Sequence ................................................. 20

DLL Constraints ......................................................... 20

Maximum Ratings ........................................................... 21

Operating Range ............................................................. 21

Electrical Characteristics ............................................... 21

DC Electrical Characteristics ..................................... 21

AC Electrical Characteristics ..................................... 22

Capacitance .................................................................... 23

Thermal Resistance ........................................................ 23

Switching Characteristics .............................................. 24

Switching Waveforms .................................................... 26

Ordering Information ...................................................... 27

Ordering Code Definitions ......................................... 27

Package Diagram ............................................................ 28

Document History Page ................................................. 29

Sales, Solutions, and Legal Information ...................... 31

Worldwide Sales and Design Support ....................... 31

Products .................................................................... 31

PSoC Solutions ......................................................... 31

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