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CY7C1020DV33-12ZSXE Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY7C1020DV33-12ZSXE Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 12 page CY7C1020DV33 Document #: 38-05461 Rev. *F Page 4 of 12 Switching Characteristics Over the Operating Range [7] Parameter Description –10 (Industrial) –12 (Automotive) Unit Min. Max. Min. Max. Read Cycle tpower[8] VCC(typical) to the first access 100 100 s tRC Read Cycle Time 10 12 ns tAA Address to Data Valid 10 12 ns tOHA Data Hold from Address Change 3 3 ns tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6ns tLZOE OE LOW to Low-Z[9] 0 0 ns tHZOE OE HIGH to High-Z[9, 10] 5 6ns tLZCE CE LOW to Low-Z[9] 3 3 ns tHZCE CE HIGH to High-Z[9, 10] 5 6ns tPU[11] CE LOW to Power-up 0 0 ns tPD[11] CE HIGH to Power-down 10 12 ns tDBE Byte Enable to Data Valid 5 6ns tLZBE Byte Enable to Low-Z 0 0 ns tHZBE Byte Disable to High-Z 5 6ns Write Cycle[12] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 8 9 ns tAW Address Set-up to Write End 8 9 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-up to Write End 5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low-Z[9] 3 3 ns tHZWE WE LOW to High-Z[9, 10] 5 6ns tBW Byte Enable to End of Write 7 8 ns Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. [+] Feedback |
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