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CY7C1020CV26 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1020CV26 Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 11 page CY7C1020CV26 512 Kb (32 K × 16) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05406 Rev. *C Revised December 14, 2010 Features ■ Temperature range ❐ Automotive: –40°C to 125°C ■ High speed ❐ tAA = 15 ns ■ Optimized voltage range: 2.5V to 2.7V ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ CMOS for optimum speed and power ■ Package offered: 44-pin TSOP II Functional Description The CY7C1020CV26 is a high performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O9 to I/O16. See the Truth Table on page 7 for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV26 is available in a standard 44-pin TSOP Type II. Logic Block Diagram [+] Feedback |
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