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CY7C1020CV33 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY7C1020CV33 Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 13 page CY7C1020CV33 Document Number: 38-05133 Rev. *H Page 6 of 13 AC Test Loads and Waveforms[4] Switching Characteristics Over the Operating Range[4] Parameter Description –10 –12 –15 Unit Min Max Min Max Min Max Read Cycle tRC Read cycle time 10 – 12 – 15 – ns tAA Address to data valid – 10 – 12 – 15 ns tOHA Data hold from address change 3–3–3– ns tACE CE LOW to data valid – 10 – 12 – 15 ns tDOE OE LOW to data valid –5–6–7 ns tLZOE OE LOW to low Z[5] 0–0–0– ns tHZOE OE HIGH to high Z[5, 6] –5–6–7 ns tLZCE CE LOW to low Z[5] 3–3–3– ns tHZCE CE HIGH to high Z[5, 6] –5–6–7 ns tPU[7] CE LOW to power-up 0–0–0– ns tPD[7] CE HIGH to power-down – 10 – 12 – 15 ns tDBE Byte enable to data valid –5–6–7 ns tLZBE Byte enable to low Z 0–0–0– ns tHZBE Byte disable to high Z –5–6–7 ns Write Cycle[8] tWC Write cycle time 10 – 12 – 15 – ns tSCE CE LOW to write end 8–9– 10 – ns tAW Address set-up to write end 7–8– 10 – ns tHA Address hold from write end 0–0–0– ns tSA Address set-up to write start 0–0–0– ns tPWE WE pulse width 7–8– 10 – ns tSD Data set-up to write end 5–6–8– ns tHD Data hold from write end 0–0–0– ns tLZWE WE HIGH to low Z[5] 3–3–3– ns tHZWE WE LOW to high Z[5, 6] –5–6–7 ns tBW Byte enable to end of write 7–8–9– ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 90% 10% 3.0 V GND 90% 10% ALL INPUT PULSES 3.3 V OUTPUT 30 pF R 317 R2 351 Rise Time: 1 V/ns Fall Time: 1 V/ns (b) (a) 3.3 V OUTPUT 5 pF (c) R 317 R2 351 High Z characteristics: [+] Feedback |
Similar Part No. - CY7C1020CV33_10 |
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Similar Description - CY7C1020CV33_10 |
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