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CY7C603XX Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY7C603XX Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 39 page  CY7C603xx Document Number: 38-16018 Rev. *L Page 4 of 39 Figure 2. Analog System Block Diagram The Analog Multiplexer System The analog mux bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Additional System Resources System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks may be generated using digital blocks as clock dividers. ■ The I2C module provides 100 kHz and 400 kHz communication over two wires. slave, master, and multi-master modes are all supported. ■ Low voltage detection interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3 voltage reference provides an absolute reference for the analog system. ■ An integrated switch mode pump generates normal operating voltages from a single 1.2 V battery cell, providing a low-cost boost converter. ■ Versatile analog multiplexer system. enCoRe III LV Device Characteristics The enCoRe III LV devices have four digital blocks and four analog blocks. Table 1 lists the resources available for specific enCoRe III LV devices. Getting Started The quickest path to understanding the enCoRe III LV silicon is by reading this data sheet and using the PSoC Designer integrated development environment (IDE). This data sheet is an overview of the enCoRe III LV and presents specific pin, register, and electrical specifications. enCoRe III LV is based on the architecture of the CY8C21x34. For in-depth information, along with detailed programming information, refer to the PSoC Programmable System-on-Chip Technical Reference Manual, which is available at http://www.cypress.com. For up-to-date ordering, packaging, and electrical specification information, refer to the latest device data sheets on the web at http://www.cypress.com. Development Kits Development kits are available from the following distributors: Digi-key, avnet, arrow, and future. The Cypress online store contains development kits, C compilers, and all accessories for enCoRe III LV development. Go to the Cypress online store web site at http://www.cypress.com. ACOL1MUX ACE00 ACE01 Array Array Input Configuration ASE10 ASE11 X X X X X AnalogMux Bus AllIO ACI0[1:0] ACI1[1:0] Table 1. enCoRe III LV Device Characteristics Part Number CY7C60323- PVXC 24 1 4 24 0 2 4 512 Bytes 8K [+] Feedback |
Similar Part No. - CY7C603XX_11 |
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Similar Description - CY7C603XX_11 |
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