CY7C199N

32 K × 8 Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 001-06493 Rev. *B

Revised December 13, 2010

Features

— 15 ns

— 550 mW (max, 15 ns “L” version)

— 0.275 mW (max, “L” version)

Functional Description

The CY7C199N is a high-performance CMOS static RAM

organized as 32,768 words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE) and active

LOW Output Enable (OE) and three-state drivers. This device

has an automatic power-down feature, reducing the power

consumption by 81% when deselected. The CY7C199NN is in

the standard 300-mil-wide DIP, SOJ, and LCC packages.

An active LOW Write Enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and Write Enable

(WE) is HIGH. A die coat is used to improve alpha immunity.

COLUMN

DECODER

INPUT BUFFER

POWER

DOWN

WE

OE

CE

1024 x 32 x 8

ARRAY

Logic Block Diagram

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