CY7C107D

CY7C1007D

Document #: 38-05469 Rev. *G

Page 5 of 11

Parameter

Description

7C107D-10

7C1007D-10

Unit

Min

Max

Read Cycle

100

s

Read Cycle Time

10

ns

Address to Data Valid

10

ns

Data Hold from Address Change

3

ns

CE LOW to Data Valid

10

ns

CE LOW to Low Z [8]

3ns

CE HIGH to High Z [8, 9]

5ns

CE LOW to Power-Up

0

ns

CE HIGH to Power-Down

10

ns

Write Cycle [11]

Write Cycle Time

10

ns

CE LOW to Write End

7

ns

Address Set-Up to Write End

7

ns

Address Hold from Write End

0

ns

Address Set-Up to Write Start

0

ns

WE Pulse Width

7

ns

Data Set-Up to Write End

6

ns

Data Hold from Write End

0

ns

WE HIGH to Low Z [8]

3ns

WE LOW to High Z [8, 9]

6ns

Notes

6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

high impedance state.

10. This parameter is guaranteed by design and is not tested.

11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these

signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

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