CY2DL1510

Document Number: 001-54863 Rev. *H

Page 5 of 15

DC Electrical Specifications

Parameter

Description

Condition

Min

Max

Unit

Operating supply current

All LVDS outputs terminated with 100

Ω

load[3, 4]

–

125

mA

Input high Voltage, LVDS input clocks,

IN and IN#

V

Input low voltage, LVDS input clocks,

IN and IN#

–0.3

–

V

Input high voltage, CLK_EN

2.0

V

Input low voltage, CLK_EN

–0.3

0.8

V

Input high voltage, CLK_EN

1.7

V

Input low voltage, CLK_EN

–0.3

0.7

V

[5]

Input differential amplitude

See Figure 3 on page 7

0.4

0.8

V

Input common mode voltage

See Figure 3 on page 7

0.5

V

Input high current, All inputs

[6]

–

150

μA

Input low current, All inputs

[6]

–150

–

μA

LVDS differential output voltage peak to

peak, single-ended

[3, 7]

250

470

mV

ΔV

OCM

output states

[3, 7]

–50

mV

Output reference voltage

0 to 150

μA output current

1.125

1.375

V

On-chip differential input termination

resistor

80

120

Ω

Internal pull-up resistance,

LVCMOS logic input

CLK_EN pin

60

140

k

Ω

Input capacitance

Measured at 10 MHz per pin

–

3

pF

Notes

3. Refer to Figure 2 on page 7.

6. Positive current flows into the input pin, negative current flows out of the input pin.

7. Refer to Figure 4 on page 7.

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