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MCIMX53XD Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc |
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MCIMX53XD Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 204 page  i.MX53xD Applications Processors for Consumer Products, Rev. 1 12 Freescale Semiconductor Modules List IOMUXC IOMUX Control System Control Peripherals This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. IPU Image Processing Unit Multimedia Peripherals Version 3M IPU enables connectivity to displays, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces: • Legacy parallel interfaces • Single/dual channel LVDS display interface • Analog TV or VGA interfaces The processing includes: • Image enhancement—color adjustment and gamut mapping, gamma correction and contrast enhancement • Video/graphics combining • Support for display backlight reduction • Image conversion—resizing, rotation, inversion and color space conversion • Hardware de-interlacing support • Synchronization and control capabilities, allowing autonomous operation. KPP Keypad Port Connectivity Peripherals The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection LDB LVDS Display Bridge Connectivity Peripherals LVDS display bridge is used to connect the IPU (image processing unit) to external LVDS display interface. LDB supports two channels; each channel has following signals: • 1 clock pair • 4 data pairs On-chip differential drivers are provided for each pair. OWIRE One-Wire Interface Connectivity Peripherals One-wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502. PATA Parallel ATA Connectivity Peripherals The PATA block is a AT attachment host interface. Its main use is to interface with hard disk drives and optical disc drives. It interfaces with the ATA-6 compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. PWM-1 PWM-2 Pulse Width Modulation Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. INTRAM Internal RAM Internal Memory Internal RAM, shared with VPU. The on-chip memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. BOOTROM Boot ROM Internal Memory Supports secure and regular boot modes. The ROM controller supports ROM patching. Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic Block Name Subsystem Brief Description |
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