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MCIMX53XD Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc |
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MCIMX53XD Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 204 page  Electrical Characteristics i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 21 4.1.4 External Clock Sources The i.MX53xD device has four external input system clocks, a low frequency (CKIL), a high frequency (XTAL), and two general purpose CKIH1 and CKIH2 clocks. The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and accurate frequencies. Table 7 shows the interface frequency requirements. 5 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 6 By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 7 In case the VDD_FUSE is kept powered on during Fuse Read mode, the efuse_prog_supply_gate bit in CCM_CGPR register should be kept low, to avoid the possibility of inadvertently blowing fuses. Alternately, VDD_FUSE can be ground or left floating, when not in Fuse Write mode. 8 If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain floating. 9 GPIO pad operational at low frequency 10 The analog supplies should be isolated in the application design. Use of series inductors is recommended. 11 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source. 12 Lifetime of 21,900 hours based on 95 C junction temperature at nominal supply voltages. Table 7. External Input Clock Frequency Parameter Description Symbol Min Typ Max Unit CKIL Oscillator1 1 External oscillator or a crystal with internal oscillator amplifier. fckil — 32.7682/32.0 2 Recommended nominal frequency 32.768 kHz. —kHz CKIH1, CKIH2 Operating Frequency fckih1, fckih2 See Table 31, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 44 MHz XTAL Oscillator fxtal 22 24 27 MHz |
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