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K50P144M100SF2 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc

Part # K50P144M100SF2
Description  Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

K50P144M100SF2 Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc

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Table 26. 16-bit ADC with PGA operating conditions (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
RPGAD
Differntial input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
128
64
32
IN+ to IN-4
RAS
Analog source
resistance
100
Ω
5
TS
ADC sampling
time
1.25
µs
6
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 27. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA
Supply current
590
TBD
μA
IDC_PGA
Input DC current
A
2
IILKG
Input Leakage
current
PGA disabled
TBD
TBD
μA
3
G
Gain4
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.98
1.99
3.97
7.95
15.8
31.4
61.2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
RAS < 100Ω
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
4
40
kHz
kHz
PSRR
Power supply
rejection ration
Gain=1
TBD
TBD
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
Table continues on the next page...
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
41


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