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K40P144M100SF2 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc |
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K40P144M100SF2 Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc |
46 / 75 page Table 27. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes CMRR Common mode rejection ratio • Gain=1 • Gain=64 TBD TBD TBD TBD — — dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 TBD mV Gain=1, ADC Averaging=32 TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over temperature • Gain=1 • Gain=64 — — TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage • Gain=1 • Gain=64 — — TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V EIL Input leakage error All modes IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing where VX = VREFPGA × 0.583 V 6 SNR Signal-to-noise ratio • Gain=1 • Gain=64 TBD TBD 83.0 57.5 — — dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion • Gain=1 • Gain=64 TBD TBD 89.4 90.0 — — dB dB 16-bit differential mode, Average=32, fin=500Hz SFDR Spurious free dynamic range • Gain=1 • Gain=64 TBD TBD 90.9 77.0 — — dB dB 16-bit differential mode, Average=32, fin=500Hz Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 46 Preliminary Freescale Semiconductor, Inc. |
Similar Part No. - K40P144M100SF2_11 |
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Similar Description - K40P144M100SF2_11 |
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