ISL6267

8

January 31, 2011

FN7801.0

16

ISEN3/FB2

When the Core VR of ISL6267 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual

current sensing for Channel 3. When the Core VR of ISL6267 is configured in 2-phase mode, this pin is

FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off

in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase

mode to achieve optimum performance.

17

ISEN2

Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to 5V VDD, the controller

disables Channel 2, and the Core VR runs in single-phase mode.

18

ISEN1

Individual current sensing for Channel 1 of the Core output.

19

VSEN

Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.

20

RTN

Output voltage sense return pin for the Core controller. Connect to the -sense pin of the microprocessor

die.

21

ISUMN

Inverting input of the transconductance amplifier for current monitor and load line of Core output.

22

ISUMP

Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.

23

VDD

5V bias power.

24

VIN

Battery supply voltage, used for feed-forward.

25

PROG1

Program pin for setting output voltage offset for Core VR.

26

BOOT1

Connect an MLCC capacitor across the BOOT1 and the phase (PH1) pin. The boot capacitor is charged

through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PH1 pin

drops below VCCP minus the voltage dropped across the internal boot diode.

27

UG1

Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UG1 pin to the gate of

the Phase 1 high-side MOSFET.

28

PH1

Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PH1 pin to the node

consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of

Phase 1.

29

LG1

Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LG1 pin to the gate of the

Phase 1 low-side MOSFET.

30

PWM3

PWM output for Channel 3 of the Core VR. When PWM3 is pulled to 5V VDD, the controller disables Phase

3 and runs in 2-phase mode.

31

VCCP

Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1µF

of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.

32

LG2

Output of the Phase 2 low-side MOSFET gate driver of VR1. Connect the LG2 pin to the gate of the

Phase 2 low-side MOSFET.

33

PH2

Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PH2 pin to

the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor

of Phase 2.

34

UG2

Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UG2 pin to the gate of

the Phase 2 high-side MOSFET.

35

BOOT2

Connect an MLCC capacitor across the BOOT2 and PH2 pins. The boot capacitor is charged through an

internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PH2 pin drops below

VCCP minus the voltage dropped across the internal boot diode.

36

PWM2_NB

PWM output for Channel 2 of the Northbridge VR.

37

LG1_NB

Output of the low-side MOSFET gate driver of the Northbridge VR. Connect the LG1_NB pin to the gate of

the low-side MOSFET of VR2.

38

PH1_NB

Current return path for the high-side MOSFET gate driver of the Northbridge VR. Connect the PH1_NB pin

to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output

inductor of the Northbridge VR.

39

UG1_NB

Output of the high-side MOSFET gate driver of the Northbridge VR. Connect the UG1_NB pin to the gate

of the high-side MOSFET.

PIN NUMBER

SYMBOL

DESCRIPTION