ISL76683

6

FN7697.1

January 31, 2011

Principles of Operation

Photodiodes

The ISL76683 contains two photodiodes. Diode1 is sensitive to

both visible and infrared light, while Diode2 is mostly sensitive to

infrared light. The spectral response of the two diodes are

independent from one another. See Figure 2 “Spectral Response” in

the “Typical Performance Curves” section. The photodiodes

convert light to current then the diodes’ current outputs are

converted to digital by a single built-in integrating type 16-bit

determines which photodiode will be converted to a digital signal.

Mode1 is Diode1 only. Mode2 is Diode2 only. Mode3 is a

sequential Mode1 and Mode2 with an internal subtract function

(Diode1 - Diode2).

Analog-to-Digital Converter (ADC)

The converter is a charge-balancing integrating type 16-bit ADC.

The chosen method for conversion is best for converting small

current signals in the presence of AC periodic noise. A 100ms

integration time, for instance, highly rejects 50Hz and 60Hz

power line noise simultaneously. See “Integration Time or

Conversion Time” on page 11 and “Noise Rejection” on page 12.

The built-in ADC offers the user flexibility in integration time or

conversion time. Two timing modes are available; Internal Timing

Mode and External Timing Mode. In Internal Timing Mode,

integration time is determined by an internal dual speed oscillator

External Timing Mode, integration time is determined by the time

“External Timing Mode” on page 10. A good balancing act of

integration time and resolution depending on the application is

required for optimal results.

dynamically accommodate various lighting conditions. For very

dim conditions, the ADC can be configured at its lowest range.

For very bright conditions, the ADC can be configured at its

highest range.

Interrupt Function

The active low interrupt pin is an open drain pull-down

configuration. The interrupt pin serves as an alarm or monitoring

function to determine whether the ambient light exceeds the

upper threshold or goes below the lower threshold. The user can

also configure the persistency of the interrupt pin. This

eliminates any false triggers, such as noise or sudden spikes in

ambient light conditions. An unexpected camera flash, for

example, can be ignored by setting the persistency to 8

integration cycles.

There are eight (8) 8-bit registers available inside the ISL76683. The

command and control registers define the operation of the device.

The command and control registers do not change until the registers

are overwritten. There are two 8-bit registers that set the high and

low interrupt thresholds. There are four 8-bit data Read Only

registers; two bytes for the sensor reading and another two bytes for

the timer counts. The data registers contain the ADC's latest digital

output, and the number of clock cycles in the previous integration

period.

internally as 1000100. When 1000100x with x as R or W is sent

after the Start condition, this device compares the first seven bits

of this byte to its address and matches.

Figure 12 shows a sample one-byte read. Figure 13 shows a sample

one-byte write. Figure 14 shows a sync_iic timing diagram sample

drives the SCL (clock) line, while either the master or the slave can

transaction begins with the master asserting a start condition (SDA

falling while SCL remains high). The following byte is driven by the

master and includes the slave address and read/write bit. The

receiving device is responsible for pulling SDA low during the

acknowledgement period.

condition (SDA rising while SCL remains high).