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SX8805Rxxx Datasheet(PDF) 5 Page - Semtech Corporation |
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SX8805Rxxx Datasheet(HTML) 5 Page - Semtech Corporation |
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5 / 156 page  © Semtech 2006 www.semtech.com 1-3 XE8805/05A INSTRUCTION MEMORY B U S C O N T R O L L E R TEST CONTROLLER RESET BLOCK WD CLOCK GENERATION/ POWER MANAGEMENT VREG XTAL RC CPU COOLRISC816 8X8 MULTIPLIER 16 CPU REGISTERS IRQ HANDLING EVN HANDLING PORT B 8 DATA REGISTERS PORT A PORT C address control datain dataout reset control clocks test control irq evn VPP/TEST VBAT VSS RESET OSCIN OSCOUT VREG PB(7:0) PA(7:0) PC(7:0) AC_R(3:0) AC_A(7:0) VMULT DAS_OUT DAS_AI_P DAS_AI_M DAS_AO DAB_R_P DAB_R_M DAB_OUT DAB_AI_P DAB_AI_M DAB_AO_P DAB_AO_M DATA MEMORY VLD USRT UART COUNTERS TIMERS PWM POR ACQUISITION CHAIN ZoomingADC TM VMULT DAS Signal D/A DAB Bias D/A Figure 1-1. Block schematic of the XE8805/05A circuit. The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous serial link. The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate interrupts or events. The PWM is output on Port B. |
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