No. 6871-11/29

LC72714W

Data Update Timing for Read Registers

The data in the two read registers (the status register at address 01H and the block number register at address 02H) is

updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point

immediately before the INT output.

In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will

be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that

data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for

the next interrupt.

If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the

additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.

Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application

checks the current reception status by reading out the status register and checking bit 6 (data received in the block

synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH)

is 0 provides superior real time characteristics.

CPU Interface Timing <Parallel Mode>

• Register Read Timing

A0 to A3

CS

Valid

output

RD

RDY

DATn