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SY89871UMG Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY89871UMG Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 10 page 1 Precision Edge® SY89871U Micrel, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 DESCRIPTION Two matched-delay outputs: • Bank A: undivided pass-through (QA) • Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1) Matched delay: all outputs have matched delay, independent of divider setting Guaranteed AC performance: • >2.5GHz fMAX • <250ps tr/tf • <670ps tpd (matched delay) • <15ps within-device skew Low jitter design • <1psRMS cycle-to-cycle jitter • <10psPP total jitter Power supply 3.3V or 2.5V Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) TTL/CMOS inputs for select and reset 100K EP compatible LVPECL outputs Parallel programming capability Wide operating temperature range: –40°C to +85°C Available in 16-pin (3mm x 3mm) MLF® package FEATURES APPLICATIONS OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards 1 Rev.: F Amendment: /0 Issue Date: August 2007 The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency- locked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A V REF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting. All support documentation can be found on Micrel’s web site at: www.micrel.com. FUNCTIONAL BLOCK DIAGRAM Precision Edge® Precision Edge® SY89871U 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/ FANOUT BUFFER W/INTERNAL TERMINATION TYPICAL PERFORMANCE Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. IN 50 Ω 50 Ω /IN S0 S1 QB1 /QB1 QB0 /QB0 QA /QA /RESET VT VREF-AC Divided by 2, 4, 8 or 16 Decoder /QB0 QB0 /QA QA QA@622MHz and QB@155.5MHz ÷4 622MHz Output 155.5MHz Output |
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