2

Precision Edge®

SY89831U

Micrel, Inc.

M9999-072210

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERINGINFORMATION

Package Operating

Package

Lead

PartNumber

Type

Range

Marking

Finish

SY89831UMI

MLF-16

Industrial

831U

Sn-Pb

MLF-16

Industrial

831U

Sn-Pb

MLF-16

Industrial 831U with Pb-Free

NiPdAu

bar-line indicator

Pb-Free

Industrial 831U with Pb-Free

NiPdAu

bar-line indicator

Pb-Free

Notes:

only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

PinNumber

PinName

PinFunction

15, 16

Q0, /Q0

Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies

1, 2,

Q1, /Q1

of the inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be

3, 4,

Q2, /Q2

5, 6

Q3, /Q3

for more details.

8

EN

This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The

synchronous enable ensures that enable/disable will only occur when the outputs are in a logic

LOW state. Note that this input is internally connected to a 25ký pull-up resistor and will default

to logic HIGH state (enabled) if left open.

9, 12

/IN, IN

Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs

accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally

terminates to a VT pin through 50ý. Note that these inputs will default to an intermediate state if

left open. Pleae refer to the “Input Interface Applications” section for more details.

10

VREF–AC

inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with

Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin

is only intended to drive its respective VT pin. If VREF-AC is used with a 2.5V supply, make

11

VT

Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The

VTpinsprovideacenter-taptoaterminationnetworkformaximuminterfaceflexibility.See“Input

Interface Applications” section for more detaiils.

13

GND

Ground. GND pins and exposed pad must be connected to the most negative potential of the

device ground.

7, 14

VCC

Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to

each VCC pin as possible.

PIN DESCRIPTION

IN

/IN

EN

Q

/Q

0

1

1

0

1

1

0

1

1

0

X

X

0

Note:

1. On next negative transition of the input signal (IN).

TRUTHTABLE