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SY89823LHITR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY89823LHITR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 8 page 1 Precision Edge® SY89823L Micrel, Inc. M9999-091908 hbwhelp@micrel.com or (408) 955-1690 FEATURES s 22 differential HSTL (low-voltage swing) output pairs s HSTL outputs drive 50 Ω to ground with no offset voltage s 3.3V core supply, 1.8V output supply for reduced power s LVPECL and HSTL inputs s Low part-to-part skew (200ps max.) s Low pin-to-pin skew (50ps max.) s Triple-buffered output enable (OE) s –40 °C to +85°C temperature range s Available in a 64-pin EPAD-TQFP The SY89823L is a high-performance bus clock driver with 22 differential High-Speed Transceiver Logic (HSTL), 1.5V compatible output pairs. The device is designed for use in low-voltage (3.3V/ 1.8V) applications that require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive- Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a three- clock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs. The SY89823L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.), performance previously unachievable in a standard product having such a high number of outputs. The SY89823L is available in a single, space-saving package, enabling a lower overall cost solution. All support documentation can be found on Micrel’s web site at: www.micrel.com. 3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR DESCRIPTION Precision Edge® SY89823L LOGIC SYMBOL CLK_SEL HSTL_CLK /HSTL_CLK LVPECL_CLK /LVPECL_CLK OE 0 1 22 22 Q0 - Q21 /Q0 - /Q21 EN ENABLE LOGIC Rev.: D Amendment: /0 Issue Date: September 2008 Precision Edge® Precision Edge is a registered trademark of Micrel, Inc. OE(1) CLK_SEL Q0-Q21 /Q0-/Q21 0 0 LOW HIGH 0 1 LOW HIGH 1 0 HSTL_CLK /HSTL_CLK 1 1 LVPECL_CLK /LVPECL_CLK Note: 1. The output enable (OE) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal. TRUTH TABLE APPLICATIONS s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications TYPICAL PERFORMANCE 0 100 200 300 400 500 600 700 800 900 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 OUTPUT FREQUENCY (GHz) Output Amplitude vs. Frequency |
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