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SY89538LHZTR Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY89538LHZTR Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 23 page Micrel, Inc. SY89538L January 2008 M9999-010808-E hbwhelp@micrel.com or (408) 955-1690 5 Pin Description Control and Configuration (continued) Pin Number Pin Name Pin Function 24 26 58 60 PEN0 PEN1 PEN2 PEN3 TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and as a frequency select pins. PENx, PSELx, and DSEL are used together; see the “LVPECL Output Post-Divider and Frequency Select Table” for proper decoding. PENx contains internal 25kΩ pull-up. When disabled, PECL0-PECL3 outputs are a logic LOW. The threshold voltage VTH = VCC/2. 46 SYNC TTL/CMOS Output Bank Synchronization Control. Internal 25kΩ pull-up. The default state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See “Synchronization” section for details. The threshold voltage VTH = VCC/2. 5 FBSEL TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay function). Internal 25kΩ pull-up. The threshold voltage VTH = VCC/2. Default is logic HIGH, and selects internal feedback. Logic HIGH: Internal feedback (from the Programmable Divider) Logic Low: External feedback (from the FBIN inputs) 28 33 35 PD_4 PD_2 PD_0 TTL/CMOS Programmable Divider-Select Control. Internal 25kΩ pull-down. Default is logic LOW. The threshold voltage VTH = VCC/2. See “Programmable-Divider Select Table” for proper decoding. 27 29 34 PD_5 PD_3 PD_1 TTL/CMOS Programmable Divider-Select Control. Internal 25kΩ pull-up. Default is logic HIGH. The threshold voltage VTH = VCC/2. See “Programmable-Divider Select Table” for proper decoding. 13, 14 PDSEL1, PDSEL0 TTL/CMOS Pre-Divider Select Input. Internal 25kΩ pull-up. This two-bit input divider scales the VCO/2 frequency. See “Pre-Divider Frequency Select Table” for proper decoding. The threshold voltage VTH = VCC/2. 22 DSEL TTL/CMOS Post-Divider Option Control. Internal 25kΩ pull-up. Default is logic HIGH. The threshold voltage VTH = VCC/2. Logic HIGH: All LVPECL and LVDS outputs operate with their respective output frequency control (PSELx, PENx, LSEL, LEN). Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL through a /1, /4, and /16 Post-Divider. See “LVPECL and LVDS Output Post-Divider and Frequency Select Table” for proper decoding. |
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