SY87729L

7

Micrel, Inc.

M9999-062807

hbwhelp@micrel.com or (408) 955-1690

Accum

Add

Sum

Modulo

Bit

0

555

1

5

5

10

10

1

10

5

15

15

1

15

5

20

20

1

20

5

25

2

0

2

577

1

7

5

12

12

1

12

5

17

17

1

17

5

22

22

1

22

5

27

4

0

4

599

1

9

5

14

14

1

14

5

19

19

1

19

5

24

1

0

1

566

1

6

5

11

11

1

11

5

16

16

1

16

5

21

21

1

21

5

26

3

0

3

588

1

8

5

13

13

1

13

5

18

18

1

18

5

23

0

0

Table 2. 5/23 Example

Note that the sequence of bits in the last column, reading

down, is the optimal pattern to generate.

The choice of repeating bit pattern reduces jitter because

a fractional-N synthesizer relies on edges temporarily not

matching, but averaging out over some time interval.

Anything that reduces the timing disparity between edges

arriving at the phase-frequency comparator will reduce jitter.

Center Frequency Trim

This circuit block generates two identical reference

voltages for the two VCO on the SY87729L. This voltage

pair can be digitally trimmed. Trimming occurs under control

of the acquisition sequencer, which trims for center frequency

of the fractional-N synthesizer only. The wrapper synthesizer

VCO is matched to the fractional-N VCO. Both VCO are fed

the same coarse adjustment voltage, and so both center

nominally at the same frequency.

An 8-bit counter implements the voltage steps. The

acquisition sequencer steps through this counter, which

changes its voltage by about 12mV per step. The coarse

input to the VCO is nominally set at 500MHz per Volt.

The acquisition sequencer exercises the center frequency

trim circuit so that the VCO control voltage ends up within

about 12mV of where it should be, were it exactly centered

for the desired output frequency.

In the general case, the pattern “101” need not change

based on the P divider value. To multiply by 14/3 instead of

11/3, for example, the same “101” pattern would be used,

but we would alternate dividing by 5 and 4, instead of dividing

by 4 and 3. The P value, in effect, represents the integer

part of the multiplication factor.

The repeating binary bit pattern really depends only on

the number of times to divide by P, and the number of

times to divide by P-1. We label the number of times to

frequency as per this formula:

fP –

Q

QQ

f

FNOUT

P–1

PP–1

REF

=×

+

⎡

⎣

⎢

⎢

⎤

⎦

⎥

⎥

In our figure two example, we multiply by 11/3, or 4 - 1/3.

MicroWire™ interface, where they exist as the 5-bit values

“qp” and “qpm1.” Both values are unsigned binary numbers.

sum is also constrained to be 31 or less. That means that the

denominator in the above formula must be 31 or less.

to zero causes frequency multiplication exactly by P. The

both set to zero.

In the general case, the length of the repeating binary bit

The SY87729L accomplishes this by implementing

Bresenham’s algorithm in hardware. To see how this works,

we need a more complicated example. Let’s say we need to

multiply by 110/23, or 5 - 5/23. In this example, P = 5,

a bit pattern of:

11111 11111 11111 11100 000

The spaces between groups of five digits are added for

but it doesn’t match P/P-1 divider edges to input edges in

the best way possible.

In fact, the best pattern, in terms of minimizing distance

between divider and reference input edges, is:

11110 11110 1110 11110 1110

Table 2 shows how Bresenham’s algorithm works. The

first column is an accumulator. It starts at zero, but otherwise

takes the result from the fourth column of the previous row.

The second column is the value to add to the accumulator

third column forms the sum. The fourth column takes the

The last column is “0” whenever the modulo changes the

sum. Note that the Table has 23 rows, before the sum is

zero, and the entire algorithm repeats itself.