SY87721LHI datasheet(6/16 Pages) MICREL

Part #	SY87721LHI

Description	CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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6 / 16 page

SY87721L

6

Micrel, Inc.

M9999-012508

hbwhelp@micrel.com or (408) 955-1690

OUTPUTS

BRD

± [Buffered Recovered Data] – Differential CML Output

The signal is either a buffered RDIN

± or RDOUTC±,

depending on the state of the BRDMX input. This allows a

user to selectively bypass the CDR or not, as warranted by

architecture. This CML output has a voltage swing of 400mV

loaded.

LFIN [Link Fault Indicate] – O.C. TTL Output

This output indicates the status of the input data stream

RDIN. Active HIGH indicates that the internal clock recovery

PLL has locked onto the incoming data stream. LFIN will go

HIGH if CD is HIGH and RDIN is within the frequency range

of the Receive PLL (as per ALRSEL). LFIN is an

asynchronous output.

RDOUTE

± [Receive Data Out] – Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

the recovered data from the input data stream (RDIN). It is

specified on the rising edge of RCLK.

RDOUTC

± [Receive Data Out] – Differential CML Output

This is the CML version of RDOUTE

±.

RCLKE

± [Receive Clock Out] – Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

the recovered clock used to sample the recovered data

(RDOUT).

RCLKC

± [Receive Clock Out] – Differential CML Output

This is the CML version of RCLKE

±.

TCLKE

± [Transmit Clock Out] – Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

either the recovered clock (CLKSEL = HIGH) used to sample

the recovered data (RDOUT) or the transmit clock of the

frequency synthesizer (CLKSEL = LOW).

TCLKC

± [Transmit Clock Out] – Differential CML Output

This is the CML version of TCLKE

±.

PLLSN+, PLLSN– [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis narrow

band PLL.

PLLSW+, PLLSW– [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis wide band

PLL.

PLLRN+, PLLRN– [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery narrow

band PLL.

PLLRW+, PLLRW– [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery wide band

PLL.

OTHERS

VCC

Supply Voltage

VCCO

Output Supply Voltage

VCCA

Analog Supply Voltage

GND

Ground

GNDA

Analog Ground

NC

These pins are for factory test, and are to be

left unconnected during normal use.

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