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SY100EP14UK4ITR Datasheet(PDF) 3 Page - Micrel Semiconductor

Part # SY100EP14UK4ITR
Description  2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL 2GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY100EP14UK4ITR Datasheet(HTML) 3 Page - Micrel Semiconductor

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3
Precision Edge®
SY100EP14U
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
n
o
it
c
n
u
F
n
i
P
CLK0, /CLK0
PECL, LVPECL, ECL, LVECL, HSTL Clock or Data Inputs.
CLK1, /CLK1
Internal 75kΩ pull-down resistors on CLK0, CLK1, and internal 75kΩ pull-up and 75kΩ pull-down resistors or
/CLK0, /CLK1. For single-ended applications, connect signal into CLK0 and/or CLK1 inputs. /CLK0, /CLK1
default condition is VCC/2 when left floating. CLK0, CLK1 default condition is LOW when left floating.
Q0 to Q4
LVPECL, PECL, ECL Differential Outputs: Terminate with 50Ω to VCC–2V. For single-ended applications,
/Q0 to /Q4
terminate the unused output with 50Ω to VCC–2V
/EN
LVPECL, PECL, ECL compatible synchronous enable: When /EN goes HIGH, the QOUT will go LOW and
/QOUT will go HIGH on the next LOW input clock transition. Includes a 75kΩ pull-down. Default state is LOW
when left floating. The internal latch is clocked on the falling edge of the input clock (CLK0, CLK1)
SEL
LVPECL, PECL, ECL compatible 2:1 Mux input signal select: When SEL is LOW, CLK0 input pair is selected.
When SEL is HIGH, CLK1 input pair is selected. Includes a 75kΩ pull-down. Default state is LOW and
CLK0 is selected.
VBB
Output Reference Voltage: Equal to VCC–1.7V (approx.), and used for single-ended input signals or
AC-coupled applications. For single-ended PECL, LVPECL applications, bypass with a 0.01µF to VCC.
For single-ended LVTTL inputs, bypass to GND. Max. sink/source current is 0.5mA.
VCC
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
VEE
Negative Power Supply: LVPECL, PECL applications, connect to GND.
CLK_SEL
Active Input
0
CLK0, /CLK0
1
CLK1, /CLK1
FUNCTION TABLE
TRUTH TABLE(1)
CLK0
CLK1
CLK_SEL
/EN
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
Note 1. On next negative transition of CLK0 or CLK1.


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