No. 5814-10/27

LC72134M

DI Control Data

No.

Control block/data

Function

Related data

1

Main PLL

programmable

divider data

P0 to P15

DVS, SNS

• Specifies the divider for the main PLL programmable divider.

This is a binary value in which P15 is the MSB. The position of the LSB changes depending on DVS and

SNS.

(* : don’t care)

* LSB: When P4 is the LSB, P0 to P3 are ignored.

2

Main PLL reference

divider data

R0 to R3

XS

• Selects the reference frequency for the main PLL

* PLL INHIBIT mode

In this mode, the main PLL programmable divider is stopped, the FMINa and AMIN pins are pulled down

to ground, and the main PLL charge pump output goes to the high-impedance state.

* Crystal oscillator stop mode

The crystal oscillator circuit is stopped.

Therefore applications must not select this mode while the sub PLL is operating.

• Crystal oscillator element selection data

XS = 0: 4.5 MHz

XS = 1: 7.2 MHz

Note that 7.2 MHz is selected after a power on reset.

DVS

SNS

LSB

Set divisor (N)

Actual divisor

1

*

P0

272 to 65535

Twice the set value

0

1

P0

272 to 65535

The set value

0

0

P4

4 to 4095

The set value

R3

R2

R1

R0

Reference frequency

0

0

0

0

100

kHz

0

0

0

1

50

0

0

1

0

25

0

0

1

1

25

0

1

0

0

12.5

0

1

0

1

6.25

0

1

1

0

3.125

0

1

1

1

3.125

1

0

0

0

10

1

0

0

1

9

1

0

1

0

5

1

0

1

1

1

1

1

0

0

3

1

1

0

1

15

1

1

1

0

PLL INHIBIT + X’tal OSC STOP

1

1

1

1

PLL INHIBIT

• These pins select the signal input to the main PLL programmable divider (FMINa or AMIN) and switch the

input frequency range.

* See the “Structure of the Programmable Divider” section for details.

DVS

SNS

Input pin

Frequency range accepted by the input pin

1

*

FMINa

10 to 160 MHz

0

1

AMIN

2 to 40 MHz

0

0

AMIN

0.5 to 10 MHz

(* : don’t care)

Continued on next page.