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LC680100A Datasheet(PDF) 5 Page - Sanyo Semicon Device |
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LC680100A Datasheet(HTML) 5 Page - Sanyo Semicon Device |
5 / 16 page LC680100A No.6830-5/16 Pin Number Pin Name I/O Function Description Pin Format 33 NMI I NMI interrupt Schmitt Input 35 P10/BGNT I/O PORT1 bit0 input. Also bus grant output. 36 P11/RAS I/O PORT1 bit1 input. Also DRAM control RAS signal out. 37 P12/CASU I/O PORT1 bit2 input. Also DRAM control CASU signal out. 38 P13/CASL I/O PORT1 bit3 input. Also DRAM control CASL signal out. 39 P14/DMXS I/O PORT1 bit4 input. Also DRAM control DMXS signal out. Schmitt Input•Tristate output 40 P15/RFREQ I/O PORT1 bit5 input. Also DRAM control RFREQ I/O. Schmitt Input•PU Output 41 P16/IRQOT I/O PORT1 bit6 input. Also IRQOT output. 42 P17/MCLK/HOLD0 I/O PORT1 bit7 input. MCLK output, HOLD state output Schmitt Input•Tristate output 44 A0/LBS I/O Bus Address bit0 or Lower byte strobe signal. 45 to 54, 56 to 69 A1to A24 I/O Bus Address bit1 to 24. 70 A25/CS5 I/O Bus Address bit25 or CS5. 71 A26/CS4 I/O Bus Address bit26 or CS4 72 A27/CS3 I/O Bus Address bit27 or CS3. Schmitt Input•Tristate output 74 to 81, 83 to 90 D0 to D15 I/O Bus data bit0 to 15 Schmitt Input•Tristate output 92 CS0 I/O CS0 93 CS1 I/O CS1 94 CS2 I/O CS2 95 CS6 I/O CS6 Schmitt Input•Tristate output 96 RD I/O Bus read signal. 97 WRU /UBS I/O Upper byte write signal or Upper byte strobe. 98 WRL /WR I/O Upper byte write signal or Write. Schmitt Input•Tristate output 99 WAIT I/O Bus cycle wait Schmitt Input•PU output 100 BREQ I Bus request. Schmitt Input |
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