RX62N Group and RX621 Group

16-Bit SDRAM Connection and Access Examples

R01AN0585EJ0202 Rev.2.02

Page 2 of 22

Feb 14, 2014

1.

Specifications

The SDRAM interface included in the RX62N and RX621 Group microcontrollers allows the direct connection of up to

128 MB (1024 Mbits) of SDRAM. This interface supports SDRAM with a CAS latency of 1 to 3 cycles.

This application note uses a Micron Technology 128 Mbit SDRAM (the 2 Mword

× 16 bit × 4 bank

MT48LC8M16A2P-75), and connects to it over a 16-bit bus.

Figure 1 shows a sample DRAM connection diagram and Table 1 lists the SDRAM specifications.

RX62N

A12-A1

D15-D0

SDCS#

RAS#

CAS#

WE#

DQM0

CKE

SDCLK

A11-A0

DQ15-DQ0

CS#

RAS#

CAS#

WE#

DQML

CKE

CLK

BA1-0

A14-A13

2

12

16

SDRAM

MT48LC8M16A2P-75

2M-word

× 16bit × 4bank

DQM1

DQMH

Figure 1 16-bit SDRAM Connection

Table 1

SDRAM Specifications

Item

Symbol

Description

Catalog number



MT48LC8M16A2P-75 (Micron Technology, Inc)

Structure



2 Mwords

× 16 bits × 4 banks

Capacity



128 MB

Row address lines



A11-A0

Column address lines



A8-A0

Auto refresh interval



4096 refresh cycles every 64 ms

CAS latency



2/3

Initialization auto refresh count



2 times

Auto refresh period

(tRFC)

66 ns (min)

Write recovery period

(tWR)

28.33 ns (min)

Precharge command period

(tRP)

20 ns (min)

Period from active command to

precharge command

(tRAS)

44 ns (min)

Delay time from active command to

read/write command

(tRCD)

20 ns (min)