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R5F562N8ADFB Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R5F562N8ADFB Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 25 page RX62N Group and RX621 Group 16-Bit SDRAM Connection and Access Examples R01AN0585EJ0202 Rev.2.02 Page 10 of 22 Feb 14, 2014 (5) Row column latency setting Since the SDRAM used in this application note has a delay time (tRCD) of 20 ns (minimum) from the point an active command is issued until a read/write command is issued, the SDRAMC row column latency will be: 20 ns (min) ≤ row column latency Since 20 ns/(1/48 MHz) = 0.96 cycles, A row column latency of at least 1 cycle must be set. To observe stipulations on the SDRAMC row active period setting bits, the following condition must be observed. Row active period ≤ row column latency + SDRAMC column latency In this application note, the row active period is set to 3 cycles and the SDRAMC column latency is also set to 3 cycles. Here, we determined the row column latency setting cycles using the above formula. Row column latency setting cycle count ≥ (3 cycles) – (3 cycles) ≥ 0 cycles However, since the row column latency setting bits (RCD[1:0]) cannot be set to 0 cycles, in this application note, this field is set to 1 cycle, or 00b. Table 6 SDRAM Timing Register (SDTR) Bit Name Setting Value Function SDRAMC column latency setting bits (CL[2:0]) 011b 3 cycles Write recovery period setting bit (WR) 1b 2 cycles Row precharge period setting bits (RP[2:0]) 000b 1 cycle Row active period setting bits (RAS[2:0]) 010b 3 cycles Row column latency setting bits (RCD[1:0]) 00b 1 cycle ACT SDRAM command PRA Data bus SDCLK ACT: Bank active command RD: Read command PRA: All banks precharge command DSL: Device deselect command DSL d0 RCD: 1 cycle CL: 3 cycles RP: 1 cycle RAS: 3 cycles Single read RD Figure 5 Read Timing |
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