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R5F562N8ADLE Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R5F562N8ADLE Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 25 page RX62N Group and RX621 Group 16-Bit SDRAM Connection and Access Examples R01AN0585EJ0202 Rev.2.02 Page 5 of 22 Feb 14, 2014 Table 3 SDRAM Initialization Auto Refresh Control Register (SDIR) Bit Name Setting Value Function Initialization auto refresh period bits (ARFI[3:0]) 0001b 4 cycles Initialization auto refresh count bits (ARFC[3:0]) 0010b 2 times Initialization precharge cycle count setting bits (PRC[2:0]) 000b 3 cycles PRA DSL RFA SDCLK SDRAM command Initialization precharge cycle DSL DSL DSL DSL RFA DSL DSL DSL SDIR.PRC: "000" = 3 cycles SDIR.ARFI: "0001" = 4 cycles SDIR.ARFC: "0010" = 2 times DSL: Device deselect command RFA: Auto refresh command PRA: All bank precharge command Initialization auto refresh cycle Initialization auto refresh cycle Figure 2 Initialization Sequence Timing |
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