RX62N Group and RX621 Group

16-Bit SDRAM Connection and Access Examples

R01AN0585EJ0202 Rev.2.02

Page 6 of 22

Feb 14, 2014

4.2

SDRAM Mode Register Settings

After SDRAM initialization, the SDRAM mode register must be set. The mode must be set once and only once after

initialization. With the RX62N SDRAMC, the SDRAM mode register can be written automatically by setting the

SDRAM mode register (SMOD). Table 4 lists the setting values.

(1) Mode register

The RX62N SDRAMC operates with a burst length of 1. Operation is not guaranteed if a burst length other then 1 is

set. This application note uses a burst length of 1, a column latency of 3 cycles, and single access mode.

Table 4

SDRAM Mode Register (SDMOD)

Bit Name

Setting Value

Function

Mode register setting bits (MR[14:0])

230h

A burst length of 1,

a column latency of 3 cycles,

and single access mode.

SDCLK

Mode register

setting cycle

MRS

DSL

SDRAM command

DSL

A

Address bus

DSL: Device deselect

MRS: Mode register setting command

3 cycles (Fixed)

Figure 3 SDRAM Mode Register Setting Timing