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ADM1166 Datasheet(PDF) 18 Page - Analog Devices

Part No. ADM1166
Description  Super Sequencer with Margining Control and Nonvolatile Fault Recording
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM1166 Datasheet(HTML) 18 Page - Analog Devices

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ADM1166
Rev. 0 | Page 18 of 32
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 28 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
three-supply system.
Table 8 lists the PDO outputs for each state in the same SE
implementation. In this system, a good 5 V supply on the VP1 pin
and the VX1 pin held low are the triggers required to start a
power-up sequence. Next, the sequence turns on the 3.3 V supply,
then the 2.5 V supply (assuming successful turn-on of the 3.3 V
supply). When all three supplies have turned on correctly, the
PWRGD state is entered, where the SE remains until a fault occurs
on one of the three supplies or until it is instructed to go through a
power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of
the sequence detector.
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX5
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
Figure 27. Sequence Detector Block Diagram
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 28, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5
PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES
TIMEOUT
STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
(VP1 +
VP2) = 0
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
Figure 28. Sample Application Flow Diagram
Table 8. PDO Outputs for Each State
PDO Outputs
IDLE1
IDLE2
EN3V3
EN2V5
DIS3V3
DIS2V5
PWRGD
FSEL1
FSEL2
PDO1 = 3V3ON
0
0
1
1
0
1
1
1
1
PDO2 = 2V5ON
0
0
0
1
1
0
1
1
1
PDO3 = FAULT
0
0
0
0
1
1
0
1
1


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