Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

PCF8576D Datasheet(PDF) 32 Page - NXP Semiconductors

Part No. PCF8576D
Description  Universal LCD driver for low multiplex rates
Download  50 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo 

PCF8576D Datasheet(HTML) 32 Page - NXP Semiconductors

Zoom Inzoom in Zoom Outzoom out
 32 / 50 page
background image
PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 14 February 2011
32 of 50
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0).
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded
PCF8576Ds contribute additional segment outputs but their backplane outputs are left
open-circuit (see Figure 22).
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed
on all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in Figure 23.
Table 17.
Addressing cascaded PCF8576D
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
100
000
0
011
0
102
0
113
1
004
1
015
1
106
1
117
210
008
0
019
0
1010
0
1111
1
0012
1
0113
1
1014
1
1115


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn