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PCF8576D Datasheet(PDF) 30 Page - NXP Semiconductors

Part No. PCF8576D
Description  Universal LCD driver for low multiplex rates
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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PCF8576D Datasheet(HTML) 30 Page - NXP Semiconductors

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PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 14 February 2011
30 of 50
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
11. Dynamic characteristics
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
Not tested in production.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
Table 16.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
fclk(int)
internal clock frequency
[1]
1440
1850
2640
Hz
fclk(ext)
external clock frequency
960
-
2640
Hz
tclk(H)
HIGH-level clock time
60
-
-
μs
tclk(L)
LOW-level clock time
60
-
-
μs
Synchronization
tPD(SYNC_N) SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
1
-
-
μs
tPD(drv)
driver propagation delay
VLCD = 5 V
[2]
--30
μs
I2C-bus[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL clock
0.6
-
-
μs
Pin SDA
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pins SCL and SDA
tBUF
bus free time between a STOP and
START condition
1.3
-
-
μs
tSU;STO
set-up time for STOP condition
0.6
-
-
μs
tHD;STA
hold time (repeated) START condition
0.6
-
-
μs
tSU;STA
set-up time for a repeated START
condition
0.6
-
-
μs
tr
rise time of both SDA and SCL signals
fSCL = 400 kHz
-
-
0.3
μs
fSCL < 125 kHz
-
-
1.0
μs
tf
fall time of both SDA and SCL signals
-
-
0.3
μs
Cb
capacitive load for each bus line
-
-
400
pF
tw(spike)
spike pulse width
on the I2C-bus
--50
ns


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