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PCF8576D Datasheet(PDF) 29 Page - NXP Semiconductors

Part No. PCF8576D
Description  Universal LCD driver for low multiplex rates
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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PCF8576D Datasheet(HTML) 29 Page - NXP Semiconductors

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PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 14 February 2011
29 of 50
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
10. Static characteristics
[1]
VLCD > 3 V for 13 bias.
[2]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3]
When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 14 (see Figure 19
too).
[4]
Propagation delay of driver between clock (CLK) and LCD driving signals.
[5]
Periodically sampled, not 100 % tested.
[6]
Outputs measured one at a time.
Table 15.
Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
[1]
2.5
-
6.5
V
IDD
supply current
fclk(ext) = 1536 Hz
[2]
-6
20
μA
VDD =3.0 V;
Tamb =25 °C
-2.7
-
μA
IDD(LCD)
LCD supply current
fclk(ext) = 1536 Hz
[2]
-18
30
μA
VDD(LCD) =3.0 V;
Tamb =25 °C
-
17.5
-
μA
Logic
VP(POR)
power-on reset supply voltage
1.0
1.3
1.6
V
VIL
LOW-level input voltage
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS
-0.3VDD
V
VIH
HIGH-level input voltage
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
[3][4]
0.7VDD
-VDD
V
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD =5 V
on pins CLK and SYNC
1-
-
mA
on pin SDA
3
-
-
mA
IOH(CLK)
HIGH-level output current on pin CLK
output source current;
VOH =4.6 V; VDD =5V
1-
-
mA
IL
leakage current
VI =VDD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
−1-
+1
μA
IL(OSC)
leakage current on pin OSC
VI =VDD
−1-
+1
μA
CI
input capacitance
[5]
--
7
pF
LCD outputs
ΔV
O
output voltage variation
on pins BP0 to BP3 and
S0 to S39
−100
-
+100
mV
RO
output resistance
VLCD = 5 V
[6]
on pins BP0 to BP3
-
1.5
-
k
Ω
on pins S0 to S39
-
6.0
-
k
Ω


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