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LPC1225FBD48321 Datasheet(PDF) 44 Page - NXP Semiconductors

Part No. LPC1225FBD48321
Description  32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
Download  60 Pages
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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LPC1225FBD48321 Datasheet(HTML) 44 Page - NXP Semiconductors

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LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 21 February 2011
44 of 60
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
11. Dynamic characteristics
11.1 Flash memory
[1]
Erase and programming times are valid over the lifetime of the device (minimum 20000 cycles).
[2]
Number of program/erase cycles.
11.2 External clock
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply
voltages.
Table 11.
Dynamic characteristic: flash memory
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
Symbol
Parameter
Conditions
Min
Max
Unit
ter
erase time
for one page (512 byte)
[1] -20
ms
for one sector (4 kB)
[1]
162
ms
for all sectors; mass
erase
[1] -20
ms
tprog
programming
time
one word (4 bytes)
[1] -49
s
four sequential words
[1] -194
s
128 bytes (one row of 32
words)
[1] -
765
s
Nendu
endurance
[2] 20000
-
cycles
tret
retention time
10
-
years
Table 12.
Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk)  0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk)  0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
Fig 18. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL
tCLCX
tCHCX
Tcy(clk)
tCLCH
002aaa907


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