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LPC1225FBD48321 Datasheet(PDF) 27 Page - NXP Semiconductors |
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LPC1225FBD48321 Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 60 page 
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 — 21 February 2011 27 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.19.3 Brownout detection The LPC122x includes four levels for monitoring the voltage on the VDD(3V3) pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip. 7.19.4 Code security (Code Read Protection - CRP) This feature of the LPC122x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the SWD and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of Code Read Protection: 1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_12 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be disabled. 7.19.5 APB interface The APB peripherals are located on one APB bus. 7.19.6 AHB-Lite The AHB-Lite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.19.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. |
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