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LPC1225FBD48321 Datasheet(PDF) 26 Page - NXP Semiconductors

Part No. LPC1225FBD48321
Description  32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
Download  60 Pages
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1225FBD48321 Datasheet(HTML) 26 Page - NXP Semiconductors

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All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 21 February 2011
26 of 60
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
The GPIO pins PIO0_0 to PIO0_11 (up to 12 pins total) and the RTC match interrupt can
serve as a wake-up input to the start logic to wake up the chip from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
Real Time Clock, the four general-purpose registers, and the WAKEUP pin. The LPC122x
can wake up from Deep power-down mode via the WAKEUP pin or the RTC match
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.19 System control
7.19.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt
vector table. The start logic pins can serve as external interrupt pins when the chip is
running. In addition, an input signal on the start logic pins can wake up the chip from
Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
7.19.2 Reset
Reset has four sources on the LPC122x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.

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