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LPC1225FBD48321 Datasheet(PDF) 16 Page - NXP Semiconductors

Part No. LPC1225FBD48321
Description  32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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LPC1225FBD48321 Datasheet(HTML) 16 Page - NXP Semiconductors

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LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 21 February 2011
16 of 60
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
[1]
After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25.
7.
Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.1.1 System tick timer
The ARM Cortex-M0 includes a System Tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
7.2 On-chip flash program memory
The LPC122x contain up to 128 kB of on-chip flash memory.
7.3 On-chip SRAM
The LPC122x contain a total of up to 8 kB on-chip static RAM memory.
7.4 Memory map
The LPC122x incorporates several distinct memory regions, shown in the following
figures. Figure 4 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
SWD
SWCLK[1]
I
PIO0_18
PIO0_26
-
SWDIO[1]
I/O
PIO0_25
PIO1_2
-
Reset
RESET
I
PIO0_13
-
-
Clockout pin
CLKOUT
O
PIO0_12
-
-
Table 4.
Pin multiplexing
Peripheral
Function
Type
Available on ports:


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