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PCA9525D Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA9525D Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 22 page PCA9525 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 25 February 2011 6 of 22 NXP Semiconductors PCA9525 Simple 2-wire bus buffer [1] Guaranteed by design, not subject to test. [2] Supply voltage dependent; refer to graphs (Figure 5 through Figure 8) for typical trend. Enable (EN) Vth(en) enable threshold voltage EN active; VDD =2.7 V 2.0 - - V EN active; VDD =5.5 V 4.8 - - V Vth(dis) disable threshold voltage EN standby; VDD = 2.7 V --0.9 V EN standby; VDD = 5.5 V --2.1 V Vhys hysteresis voltage VDD =2.7 V 100 - - mV VDD =5.5 V 200 - - mV ILI input leakage current VI = VDD -- ±0.1 μA Direction (DIR) VI(dir) direction input voltage direction SCL_OUT to SCL_IN VDD =2.7 V 2.0 - - V VDD =5.5 V 4.8 - - V direction SCL_IN to SCL_OUT VDD = 2.7 V - - 0.9 V VDD = 5.5 V - - 2.1 V Vhys hysteresis voltage VDD =2.7 V 100 - - mV VDD =5.5 V 200 - - mV ILI input leakage current VI =VDD -- ±0.1 μA Timing characteristics (Figure 4) td delay time RPU = 620 Ω [1] -17 - ns tf fall time RPU = 620 Ω [1] -3.5 - ns Table 4. Characteristics …continued Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Fig 4. Timing diagram 002aaf332 tf td VI2C-bus time 70 % VDD 30 % VDD Sxx_IN Sxx_OUT 30 % VDD |
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