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LPC1224FBD64121 Datasheet(PDF) 20 Page - NXP Semiconductors |
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LPC1224FBD64121 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 60 page  LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 — 21 February 2011 20 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 7.10.1 Features • 16-byte Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto-baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode (UART0). • Support for modem control (UART0). 7.11 SSP/SPI serial I/O controller The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.11.1 Features • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 7.12 I2C-bus serial I/O controller The LPC122x contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 Features • The I2C-interface is a standard I2C-compliant bus interface with open-drain pins and supports I2C Fast-mode Plus with bit rates of up to 1 Mbit/s. • Programmable digital glitch filter providing a 60 ns to 1 s input filter. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. |
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