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LPC2470FET208 Datasheet(PDF) 46 Page - NXP Semiconductors |
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LPC2470FET208 Datasheet(HTML) 46 Page - NXP Semiconductors |
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46 / 89 page  LPC2470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 14 February 2011 46 of 89 NXP Semiconductors LPC2470 Flashless 16-bit/32-bit microcontroller level, starts the wake-up timer (see description in Section 7.25.3 “Wake-up timer”), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, and a fixed number of clocks have passed. Once the internal reset is removed, all of the processor and peripheral registers have been initialized to predetermined values and the LPC2470 continues with booting from an external static memory. 7.26.2 Boot process The processor always boots from the off-chip static memory bank 1, executing code from address 0x8100 0000 (see Table 5 “LPC2470 memory usage and details”). During the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled, and the external memory banks 0 and 1 are configured with the same data bus width. The data bus width is determined by the setting of the two boot pins. Unused address pins are configured as GPIO. See Section 14.2 “Suggested boot memory interface solutions” for address and data bus interface details. Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped. The user code residing in the external boot memory must be linked to execute from address location 0x8000 0000. When booting from external memory, the interrupt vectors are mapped to the bottom of the external memory. Once booting is over, the application must map interrupt vectors to the proper domain. 7.26.3 Brownout detection The LPC2470 includes 2-stage monitoring of the voltage on the VDD(DCDC)(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2470 when the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 7.26.4 AHB The LPC2470 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. |
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